|
|
Software Pipelining in the LLVM Compiler
Glasnák, Ondrej ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
This thesis discusses a design and implementation of the Software Pipelining, a optimization technique of loops in a program, which tries to exploit instruction-level parallelism. It is achieved by scheduling instructions in a way to overlap iterations of the loop and therefore execute them in a pipeline. This way optimization speeds up the final program. There is a detailed description of design and implementation of Swing Modulo Scheduling algorithm, an effective and efficient method for finding near-optimal plans for software-pipelined loops. This work has been done as a part of a larger project, the development of Codasip Framework. Part of this framework is the retargetable C compiler based on compiler architecture LLVM, in which this work is implemented.
|
|
|
Compilation of OpenCL Applications for Embedded Systems
Šnobl, Pavel ; Čekan, Ondřej (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
|
|
|
Implementation of Generic Processor in FPGA
Mikušek, Petr ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis studies processor architectures suitable for embedded processors. This includes Transport Triggered Architectures (TTA). TTA is programmed by specifying data transport; operations are triggered as a side effect of data transports. In traditional Operation Triggered Architectures (OTA) requested operations are determined by program. Data transports are handled internally by hardware so it's impossible to control and optimize data transfer by compiler. This approach brings an advantage of hardware and software aspects. The aim of this thesis is to design and implement a sample TTA processor in VHDL followed by realization in FPGA. This processor is designed in a generic manner, i.e. customized by set of generic parameters such as data width, number of buses, etc.
|
|
|
Software Pipelining in the LLVM Compiler
Glasnák, Ondrej ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
This thesis discusses a design and implementation of the Software Pipelining, a optimization technique of loops in a program, which tries to exploit instruction-level parallelism. It is achieved by scheduling instructions in a way to overlap iterations of the loop and therefore execute them in a pipeline. This way optimization speeds up the final program. There is a detailed description of design and implementation of Swing Modulo Scheduling algorithm, an effective and efficient method for finding near-optimal plans for software-pipelined loops. This work has been done as a part of a larger project, the development of Codasip Framework. Part of this framework is the retargetable C compiler based on compiler architecture LLVM, in which this work is implemented.
|
|
|
Compilation of OpenCL Applications for Embedded Systems
Šnobl, Pavel ; Čekan, Ondřej (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
|
|
|
Implementation of Generic Processor in FPGA
Mikušek, Petr ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis studies processor architectures suitable for embedded processors. This includes Transport Triggered Architectures (TTA). TTA is programmed by specifying data transport; operations are triggered as a side effect of data transports. In traditional Operation Triggered Architectures (OTA) requested operations are determined by program. Data transports are handled internally by hardware so it's impossible to control and optimize data transfer by compiler. This approach brings an advantage of hardware and software aspects. The aim of this thesis is to design and implement a sample TTA processor in VHDL followed by realization in FPGA. This processor is designed in a generic manner, i.e. customized by set of generic parameters such as data width, number of buses, etc.
|
|
|
Optimizations in C Compiler for VLIW Architectures
Baručák, Robert ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
Presented is implementation of algorithm for alias analysis, which was integrated into LLVM framework. Properties and limitations of various alias analysis algorithms are discussed. Demonstrated are different approaches to working with predicates and integration of these principles with LLVM. One of the outcomes of this master's thesis is design and implementation of algorithm for profile guided if-conversion.
|
guest ::
